1. Field of the Invention
The present invention relates to the field of solid state devices, and more particularly to the processing of capacitors, resistors and other circuit devices in integrated circuits.
2. Background of the Invention
Capacitors are typically made of two parallel conductive plates that are separated by an insulator. The insulator may be air or some other suitable dielectric material. Capacitors such as MOS ("metal-oxide-semiconductor") capacitors are formed in solid state devices such as integrated circuits ("IC's") by depositing conductive regions (formed for example of aluminum or some other conductive material) on the surface of an insulating layer (for example silicon dioxide) formed over a conductive substrate (such as doped silicon). The aluminum and conductive substrate act as the charge storing plates of a capacitor, separated by the dielectric insulating layer. Capacitors can also be formed using doped polysilicon as plates as well as silicon nitride or sandwiches of silicon nitride and silicon dioxide as the insulating layer.
The capacitance of a capacitor is related to the surface area of its conductive regions or plates. Because of variability inherent in the IC fabrication process, it is difficult to precisely control the area of a conductive region being formed. FIG. 1 illustrates a capacitor cell 100 of side lengths X and Y and a dimensional variations dX and dY that can occur during processing. These variations are typically on the order of between zero plus or minus 1 micron. Because of these variations, it is difficult to manufacture IC's with capacitors having completely accurate capacitance values and ratios.
The performance of certain circuits, for example switched capacitor filter circuits, do not depend as much on the absolute values of the capacitors in the circuit as on the ratios between capacitors. Because the dimensional variations created by the manufacturing process generally affect all areas of an IC being manufactured, capacitor ratios do not vary as much as the actual capacitor dimensions and absolute capacitances. That is especially true if the conductive surfaces of each of the ratioed capacitors have the same perimeter to area ratio.
To design capacitors related to one another according to desired capacitor ratios, the concept of a unit cell is commonly used. A unit cell is a conductive layer having a standard, predetermined size and shape, typically a square. All capacitors on an IC that are to be related to each other by predetermined capacitor ratios are made of groups or arrays of electrically interconnected whole or partial unit cells. Since the cells are all nominally the same size and shape, the capacitors each ideally have the same approximate perimeter to area ratio. FIGS. 2A-C show three capacitors. Capacitor 200 is made up of a single unit cell. Capacitor 210 is made up of two unit cells, and capacitor 220 is made up of four unit cells. The capacitance ratio (also referred to as the "capacitor ratio") for any two capacitors is equal to the ratio of the number of unit cells of each. For example, the capacitance ratio of capacitor 220 to capacitor 200 is 4:1 or 4(4 unit cells versus 1 unit cell). The capacitance ratio of capacitor 220 to capacitor 210 is 2:1 or 2(4 unit cells versus 2 unit cells).
In addition to the generalized dimensional variability that occurs in the manufacturing of IC's discussed above that affects all areas of an IC substantially equally (and which, as discussed above, allows capacitor ratios to be more precise than the underlying capacitors), there are additional local effects that cause variability in capacitor ratios. One of these effects is perimeter edge shrinkage, which affects the unbounded (or "exposed") outside perimeter edges of the unit cells making up a capacitor. With respect to capacitor 220 in FIG. 2C this shrinkage occurs along exposed perimeter edges 222a to 222h, but not along inside perimeter edges 224a to 224h. For a unit cell having a side dimension of about 30 microns, the amount of exposed perimeter edge shrinkage is typically between 0 and 0.1 microns. The unit cell of capacitor 200 has only exposed perimeter edges. Accordingly, edge shrinkage is experienced by all four edges.
FIGS. 3A-B compare the edge shrinkage that occurs in the single unit cell of capacitor 200 to the edge shrinkage that occurs in one of the unit cells of capacitor 220, namely top right hand unit cell 220a. In FIGS. 3A-B, "L" represents the nominal dimension of a unit cell, and "dL" represents the shrinkage that occurs at an exposed edge. The single unit cell of capacitor 200 experiences shrinkage along all four edges. The area of the unit cell after shrinkage is (L-2dL).sup.2. Unit cell 220a of capacitor 220 only experiences shrinkage along two of its edges. The area of unit cell 220a after shrinkage is therefore (L-dL).sup.2. Because of the edge shrinkage effects, the ratio between the unit cell of capacitor 200 and unit cell 220a of capacitor 220 is not equal to unity, but is instead equal to (L-2dL).sup.2 /(L-dL).sup.2. The actual ratio depends on the magnitude of the nominal cell size L and the amount of shrinkage dL.
The approach used in the prior art to counteract the effects of unit cell edge shrinkage is illustrated in FIGS. 4A-B. "Guard rings" 420 and 440 consisting of passive "dummy" unit cells 400 are created around each capacitor, in this case capacitors 410 (one unit cell) and 430 (four unit cells). A dummy unit cell is a unit cell that is substantially the same as the unit cells of a capacitor except that it is not electrically connected to the other unit cells of the capacitor. The guard rings form a protective barrier or shield around the unit cells of the capacitor, effectively preventing edge shrinkage from the exposed edges of the capacitor.
Although the guard rings used in the prior art minimize the effects on capacitor ratios caused by cell edge shrinkage, guard rings occupy a large amount of scarce IC surface area. For example, guard ring 420 in FIG. 4A is made up of eight dummy unit cells, while capacitor 410 itself is made of only one. Guard ring 420 therefore occupies eight times as much surface area as capacitor 410. In a similar manner, guard ring 440 (made up of 12 dummy unit cells) occupies three times as much surface area as capacitor 430 (made up of four unit cells).